High data reliability, high speed of processing and data access, and reduced apparatus size are features that are demanded from electronic apparatuses. In recent years, there has been an effort to reduce a size of a printed circuit board inside electronic devices. As part of that effort to reduce the size, the printed circuit board may be manufactured to include multiple circuit layers of integrated circuits and surface components densely mounted or embedded.
When a size is reduced, a plurality of vias for power supply across layers of the printed circuit board may be densely located in each layer. Typically, the plurality of vias may be coupled to a power supply pin of an electronic component to supply power to the electronic component, and the plurality of vias may be located around the power supply pin of the electronic component. If one via of the plurality of vias may be located closer to the power supply pin among the plurality of vias, an impedance of a path (e.g., wiring, etc.) between the power supply pin and the one via may be lower which causes a higher current stressed on the path that leads to overheat or damage to surrounding components on the printed circuit board. In order to prevent such overheat or damage, a layout of the printed circuit board was designed to include the plurality of vias for power supply having a substantially equal electrical distance from the power supply pin in a manner that impedances between the power supply pin and the plurality of vias become substantially the same. However, the plurality vias with the substantially equal impedance by using the same wiring, located at the same distance from the power supply pin on a same layer may cause an obstacle for optimization of mounting a number of components densely on a limited space of the printed circuit board.
Another attempt to prevent such overheat or damage was to provide a layout of the printed circuit board with arrangements of power voltage supply regions on layers. FIG. 1A is a schematic diagram of a conventional printed circuit board 1 including a plurality of layers 10, 20, 30 and 40 and a plurality of vias 5 to 8. FIGS. 1B-1E are simplified layout diagrams of the plurality of layers 10, 20, 30 and 40 of the conventional printed circuit board 1. In particular, FIG. 1A is a side view of the printed circuit board 1 including the plurality of vias 5 to 8 coupled to a power voltage supply region 15 which provides a power supply voltage to a power supply pin 13 of an electronic component 11. The plurality of vias 5 to 8 are coupled to power voltage supply regions 32 and 41 on the layers 30 and 40, which maintain the same power voltage. Vias 9a and 9b are coupled to other voltage supply region 21 and 31 on the layers 20 and 30, which may function as a negative power supply (e.g., ground). The electronic component 11 also includes pins 12 and 14 on sides of the power supply pin 13, which transmit and receive other signals through wirings 16a and 16b. An area where the vias 5-8 are arranged is surrounded by wirings 16a and lob. Because of the wirings 16a and 16b coupled to the pins 12 and 14, the vias 6-8 and the via 5 cannot be arranged at an equal distance from the power supply pin 13, which cannot avoid the concentration of current into the via 5.
Thus, a different optimizing scheme for locating a plurality of vias to be coupled to a power supply pin may be desired.